1. Field of the Invention
The present invention relates to signal generation circuits utilizing an externally provided frequency reference signal, and particularly relates to phase locked loop circuits utilizing an externally provided reference clock.
2. Description of the Related Art
Many integrated circuits having a phase locked loop (PLL) utilize an externally provided reference clock to aid in frequency acquisition of the phase locked loop. Frequently the internal voltage controlled oscillator (VCO) within the PLL is divided down and compared to the externally provided reference clock using a frequency detector, thereby assisting the phase locked loop to xe2x80x9clockxe2x80x9d at a frequency which is a multiple of the reference clock. In some cases the frequency of the reference clock may be chosen to be one of several possible frequencies, and the internal VCO operates at the same frequency, irrespective of which one of the reference clock frequencies is provided. In this case the divider which generates the divided-down VCO clock must change its divide value to properly generate a clock having a frequency nominally equal to the external reference clock. In other cases the VCO may always operate at a fixed multiple of the externally provided reference clock. Nonetheless, it may still be desirable to know which of the possible reference clock frequencies is being provided to the device so that, for example, certain characteristics of the phase locked loop may be optimized for the particular frequency of operation.
Traditionally, integrated circuit devices which may be operated with more than one reference clock frequency include one or more additional external input pins to communicate to the device which of the frequencies is being provided to the device. For example, if any of four different reference clock frequencies may be used, two additional input pins are traditionally provided to the device, and a binary code is conveyed on the pair of pins to identify which of the reference clock frequencies is presented to the device.
Unfortunately, integrated circuit pins are a valuable resource for many integrated circuit devices and allocating two of such pins for a reference clock select function may result in fewer pins available for other, more important functionality requirements, or worse, may simply not be available to allocate at all. Even if extra integrated circuit pins are available for a reference clock select function, the board design or other aspects of the system design are, in all likelihood, more complicated.
One particular application area in which the integrated circuit package size is critical is fiber optic transmit and receive electronics that recover timing and drive the optics for serial data communication applications. One example of such a circuit includes a clock and data recovery circuit, which may be housed within an optical module housing where space is very critical.
What is desired is an improved technique which allows such devices to receive a reference clock having a frequency equal to one of several possible reference frequencies without requiring the use of dedicated reference clock select input pins.
Many types of voltage controlled oscillators (VCOs) have fairly well controlled free-running frequencies. For example, an LC-tank oscillator may have a free-running frequency controlled to within plus or minus a few percent. Other types of VCOs may be calibrated during manufacture (e.g., laser trimming) to result in a free-running frequency which is fairly well controlled within a predictable range.
Such a VCO may be used as a rough frequency standard to measure the externally provided frequency reference signal to determine its value from a finite number of discrete possible frequencies if they are sufficiently different in frequency to allow them to be distinguished using the VCO as the frequency standard. If the VCO has a frequency range which varies less, as a percentage, than the ratio between possible reference frequency values, then the VCO may be used as a frequency reference to measure the frequency reference signal. An internal signal may consequently be generated to indicate to remaining circuitry which of the possible reference frequencies is actually being provided, without requiring use of any dedicated input pins to receive a select signal.
Such an integrated circuit device may be configured for different modes of operation as a function of which reference frequency is provided to the device. Moreover, if one of the available reference clock frequencies is chosen to correspond to an internal test mode, the device may be placed in a test mode without requiring any additional dedicated input signals for that purpose either.
In one embodiment of the present invention, an integrated circuit includes a signal generation circuit responsive to an externally provided frequency reference signal having a frequency substantially equal to any of at least two possible reference frequencies. The signal generation circuit is included for generating an output signal related to the frequency reference signal. A frequency detection circuit responsive to the externally provided frequency reference signal is also included for determining which of the at least two possible reference frequencies is present, and for generating a control signal accordingly.
In another embodiment of the present invention an integrated circuit includes a phase locked loop circuit having an input for receiving an externally provided reference clock signal having a frequency substantially equal to any of at least two possible reference frequencies, and for generating a VCO output signal having a frequency related to that of the reference clock signal. The integrated circuit includes a frequency detection circuit for determining, absent any additional externally provided signal to so indicate, which of the at least two possible reference clock frequencies is present, and for communicating an indication thereof to the phase locked loop circuit.
In certain embodiments at least one of the possible reference clock frequencies corresponds to a normal operating mode of the device, and at least one of the possible reference clock frequencies corresponds to a test mode of the device.
A method embodiment of the present invention is suitable for use in an integrated circuit which is responsive to an externally provided frequency reference signal having a frequency substantially equal to any of at least two possible reference frequencies, in which the integrated circuit requires a different internal configuration depending upon which reference frequency is provided. A method of eliminating at least one external pin otherwise required to convey to the integrated circuit an external signal for indicating which reference frequency is provided, includes the steps of: (1) generating on the integrated circuit an internal signal having a frequency within a predetermined range; (2) comparing the externally provided frequency reference signal to the internal signal, to determine which reference frequency is provided; (3) generating at least one control signal as a result of the comparing step to indicate which reference frequency is provided; and (4) configuring the integrated circuit in accordance with the at least one control signal.
In a system including an integrated circuit responsive to an externally provided frequency reference signal, the integrated circuit having at least two possible modes of operation, a method of communicating a selected mode of operation to the integrated circuit includes the steps of providing to the integrated circuit an external frequency reference signal with a frequency substantially equal to a first reference frequency to select a first mode of operation, and providing to the integrated circuit an external frequency reference signal with a frequency substantially equal to a second reference frequency to select a second mode of operation.
In certain embodiments the first mode of operation is a normal operating mode and the second mode of operation is a test mode. In other embodiments the first and second modes of operation are both normal operating modes.